PM7375-SC datasheet(131/430 Pages) PMC

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PM7375 LASAR-155

DATA SHEET

PMC-931127

ISSUE 6

LOCAL ATM SAR & PHYSICAL LAYER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

115

10.1.8 Register 0x07 (0x01C): LASAR-155 Clock Recovery Control and Status

Bit

Type

Function

Default

Bit 15

TBUS[2]

Bit 14

TBUS[1]

Bit 13

TBUS[0]

Bit 12

RROOLV

Bit 11

Unused

Bit 10

Unused

Bit 9

Unused

Bit 8

Unused

Bit 7

Unused

Bit 6

Unused

Bit 5

Unused

Bit 4

Unused

Bit 3

RDOOLV

Bit 2

Unused

Bit 1

Unused

Bit 0

R/W

RREFSEL

This register controls the clock recovery and reports the state of the receive phase

locked loop.

RREFSEL:

The receive reference select (RREFSEL) bit determines the expected frequency

of RRCLK+/-. If RREFSEL is a logic 0, the reference frequency is 19.44 MHz. If

RREFSEL is a logic 1, the reference frequency must be 6.48 MHz. RREFSEL

only has effect if the RBYP bit in the LASAR-155 Master Configuration register is

low.

RDOOLV:

The receive data out of lock status indicates the clock recovery phase locked

loop is unable to lock to the incoming data stream. RDOOLV is a logic one if the

divided down recovered clock frequency not within 488 ppm of the RRCLK+/-

frequency or if no transitions have occurred on the RXD+/- inputs for more than

80 bit periods.

RROOLV:

The receive reference out of lock status indicates the clock recovery phase

locked loop is unable to lock to the receive reference (RRCLK+/-). RROOLV

should be polled after a power up reset to determine when the CRU PLL is

PM7375-SC Datasheet(PDF) 131 Page - PMC-Sierra, Inc

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