PCM5142 datasheet(46/123 Pages) TI2

46 / 123 page

SCK

BCK

SREF (Pg0, Reg 13 0x0D)

PLL

K * R / P

K = J.D

J = 1,2,3,…..,62,63

D= 0000,0001,….,9998,9999

R= 1,2,3,4,….,15,16

P= 1,2,….,127,128

PLLCK

SCK

PLLEN (Pg0, Reg 4 0x04)

PLLCKIN

GPIO *

DAC

CLK

Source

Mux

Divider

SCK

GPIO*

DSPCK (miniDSP Clock )

DACCK (DAC Clock )

SDAC (Pg0, Reg 14

0x0E)

Divider

CPCK (Charge Pump Clock )

Divider

Divide

by 2

MUX

OSRCK (Oversampling Ratio Clock )

DDSP (Pg0, Reg 27 0x1B)

DDAC (Pg0, Reg 28 0x1C)

DNCP (Pg0, Reg 29 0x1D)

DOSR (Pg0, Reg 30 0x1E)

I16E (Pg0, Reg 34 0x22)

Serial Audio

Interface

(Input)

miniDSP

(inc interpolator)

Delta

Sigma

Modulator

Current

Segments

Line Driver

fS (24bit)

16fS (24bit)

128fS (~8 bit)

-3v3 Charge

Pump

CPCK

-3V3

PCM5141, PCM5142

SLAS759B – AUGUST 2012 – REVISED JANUARY 2016

www.ti.com

8.3.6 Reset and System Clock Functions

8.3.6.1 Clocking Overview

The PCM514x devices have flexible systems for clocking. Internally, the device requires a number of clocks,

mostly at related clock rates to function correctly. All of these clocks can be derived from the serial audio

interface in one form or another.

Figure 64. Audio Flow with Respective Clocks

As shown in Figure 64 the data flows at the sample rate (fS). Once the data is brought into the serial audio

interface, it gets processed, interpolated and modulated all the way to 128 × fS before arriving at the current

segments for the final digital to analog conversion.

The clock tree is shown in Figure 65.

Figure 65. PCM514x Clock Distribution Tree

The serial audio interface typically has 4 connections: SCK (system master clock), BCK (bit clock), LRCK (left

right word clock), and DIN (data). The device has an internal PLL that is used to take either SCK or BCK and

create the higher rate clocks required by the interpolating processor and the DAC clock. This allows the device to

operate with or without an external SCK.

In situations where the highest audio performance is required, it is suggested that the SCK is brought to the

device, along with BCK and LRCK. The device should be configured so that the PLL is only providing a clock

source to the miniDSP. By ensuring that the DACCK (DAC Clock) is being driven by the external SCK source,

jitter evident in the PLL (in all PLLs) is kept out of the DAC, charge pump, and oversampling system.

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