PCM5142 datasheet(10/123 Pages) TI2

10 / 123 page

PCM5141, PCM5142

SLAS759B – AUGUST 2012 – REVISED JANUARY 2016

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7.6 Timing Requirements: SCK Input

Figure 1 shows the timing requirements for the system clock input. For optimal performance, use a clock source with low

phase jitter and noise.

MIN

NOM

MAX

UNIT

tSCY

System clock pulse cycle time

1000

DVDD = 1.8 V

tSCKH

System clock pulse width, high

DVDD = 3.3 V

DVDD = 1.8 V

tSCKL

System clock pulse width, low

DVDD = 3.3 V

7.7 Timing Requirements: PCM Audio Data

MIN

NOM

MAX

UNIT

tBCY

BCK Pulse Cycle Time

tBCL

BCK Pulse Width LOW

tBCH

BCK Pulse Width HIGH

tBL

BCK Rising Edge to LRCK Edge

tBCK

BCK frequency at DVDD = 3.3 V

24.576

MHz

tBCK(1.8V)

BCK frequency at DVDD = 1.8 V

12.288

MHz

tLB

LRCK Edge to BCK Rising Edge

tDS

DATA Set Up Time

tDH

DATA Hold Time

tDOD

DATA delay time from BCK falling edge

7.8 Timing Requirements: I

2S Master

MIN

NOM

MAX

UNIT

tBCY

BCK Pulse Cycle Time

tBCL

BCK Pulse Width LOW

tBCH

BCK Pulse Width HIGH

tBCK

BCK frequency at DVDD = 3.3 V

24.576

MHz

tBCK(1.8V)

BCK frequency at DVDD = 1.8 V

12.288

MHz

tLRD

LRCKx delay time from BCKx falling edge

–10

tDS

DATA Set Up Time

tDH

DATA Hold Time

tDOD

DATA delay time from BCK falling edge at DVDD = 3.3 V

tDOD(1.8V)

DATA delay time from BCK falling edge at DVDD = 1.8 V

7.9 Timing Requirements: XSMT

MIN

NOM

MAX

UNIT

Rise time

Fall time

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