PCM5142 datasheet(80/123 Pages) TI2

80 / 123 page

PCM5141, PCM5142

SLAS759B – AUGUST 2012 – REVISED JANUARY 2016

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RSV

Reserved

Reserved. Do not access.

GREF[2:0]

GPIO Source for PLL reference clk

These bits select the GPIO pins as clock input source when GPIO is selected as the PLL reference clock

source.

Default value: 000

This register requires use of the Clock Flex Register.000: GPIO1

001: GPIO2

010: GPIO3

011: GPIO4

100: GPIO5

101: GPIO6

others: Reserved (muted)

Table 68. Page 0 / Register 19

Dec

Hex

RSV

RQSY

Reset Value

RSV

Reserved

Reserved. Do not access.

RQSY

Sync request

This bit, when set to 1 will issue the clock resynchronization by synchronously resets the DAC, CP and OSR

clocks. The actual clock resynchronization takes place when this bit is set back to 0, where the DAC, CP and

OSR clocks are resumed at the beginning of the audio frame.

Default value: 0

0: Resume DAC, CP and OSR clocks synchronized to the beginning of audio frame

1: Halt DAC, CP and OSR clocks as the beginning of resynchronization process

Table 69. Page 0 / Register 20

Dec

Hex

RSV

PPDV3

PPDV2

PPDV1

PPDV0

Reset Value

RSV

Reserved

Reserved. Do not access.

PPDV[3:0]

PLL P

These bits set the PLL divider P factor. These bits are ignored in clock auto set mode.

Default value: 0000

0000: P=1

0001: P=2

...

1110: P=15

1111: Prohibited (do not set this value)

Table 70. Page 0 / Register 21

Dec

Hex

RSV

PJDV5

PJDV4

PJDV3

PJDV2

PJDV1

PJDV0

Reset Value

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