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PCM5142 Datasheet(PDF) 57 Page - Texas Instruments

Part # PCM5142
Description  PCM514x 2-VRMS DirectPath™, 112/106-dB Audio Stereo DAC With 32-bit, 384-kHz PCM Interface
PDF  123 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

PCM5142 Datasheet(HTML) 57 Page - Texas Instruments

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background image
t
BUF
t
S-HD
t
LOW
t
D-SU
t
D-HD
t
SCL-F
t
SCL-R
t
RS-HD
t
RS-SU
t
SP
t
P-SU
SDA
SCL
t
HI
START
Repeated
START
STOP
t
SDA-R
t
SDA-F
PCM5141, PCM5142
www.ti.com
SLAS759B – AUGUST 2012 – REVISED JANUARY 2016
Table 40. Write Operation - Basic I2C Framework
Transmitter
M
M
M
S
M
S
M
S
S
M
Data Type
St
slave address
R/
ACK
DATA
ACK
DATA
ACK
ACK
Sp
Table 41. Read Operation - Basic I2C Framework
Transmitter
M
M
M
S
S
M
S
M
M
M
Data Type
St
slave address
R/
ACK
DATA
ACK
DATA
ACK
NACK
Sp
M = Master Device; S = Slave Device; St = Start Condition; Sp = Stop Condition
8.4.1.1.2.4
Write Register
A master can write to any PCM514x registers using single or multiple accesses. The master sends a PCM514x
slave address with a write bit, a register address with auto-increment bit, and the data. If auto-increment is
enabled, the address is that of the starting register, followed by the data to be transferred. When the data is
received properly, the index register is incremented by 1 automatically. When the index register reaches 0x7F,
the next value is 0x0. Table 42 shows the write operation.
Table 42. Write Operation
Transmitter
M
M
M
S
M
S
M
S
M
S
S
M
reg
write
write
Data Type
St
slave addr
W
ACK
inc
ACK
ACK
ACK
ACK
Sp
addr
data 1
data 2
M = Master Device; S = Slave Device; St = Start Condition; Sp = Stop Condition; W = Write; ACK =
Acknowledge
8.4.1.1.2.5
Read Register
A master can read the PCM514x register. The value of the register address is stored in an indirect index register
in advance. The master sends a PCM514x slave address with a read bit after storing the register address. Then
the PCM514x transfers the data which the index register points to. When auto-increment is enabled, the index
register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 43
shows the read operation.
Table 43. Read Operation
Transmitter
M
M
M
S
M
S
M
M
M
S
S
M
M
M
slave
reg
slave
Data Type
St
W
ACK
inc
ACK
Sr
R
ACK
data
ACK
NACK
Sp
addr
addr
addr
M = Master Device; S = Slave Device; St = Start Condition; Sr = Repeated Start Condition; Sp = Stop Condition;
W = Write; R = Read; NACK = Not acknowledge
8.4.1.1.2.6
Timing Characteristics
Figure 76. Register Access Timing
Copyright © 2012–2016, Texas Instruments Incorporated
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