PCM5142 datasheet(84/123 Pages) TI2

84 / 123 page

PCM5141, PCM5142

SLAS759B – AUGUST 2012 – REVISED JANUARY 2016

www.ti.com

1: 16x interpolation

FSSP[1:0]

FS Speed Mode

These bits select the FS operation mode, which must be set according to the current audio sampling rate.

These bits are ignored in clock auto set mode.

Default value: 00

00: Single speed (FS

≤ 48 kHz)

01: Double speed (48 kHz < FS

≤ 96 kHz)

10: Quad speed (96 kHz < FS

≤ 192 kHz)

11: Octal speed (192 kHz < FS

≤ 384 kHz)

Table 81. Page 0 / Register 35

Dec

Hex

IDAC15

IDAC14

IDAC13

IDAC12

IDAC11

IDAC10

IDAC9

IDAC8

Reset Value

Table 82. Page 0 / Register 36

Dec

Hex

IDAC7

IDAC6

IDAC5

IDAC4

IDAC3

IDAC2

IDAC1

IDAC0

Reset Value

IDAC[15:0]

IDAC (MSB)

These bits specify the number of DSP clock cycles available in one audio frame. The value should match the

DSP clock FS ratio. These bits are ignored in clock auto set mode.

Default value: 0000000100000000

Table 83. Page 0 / Register 37

Dec

Hex

RSV

IDFS

IDBK

IDSK

IDCH

IDCM

DCAS

IPLK

Reset Value

RSV

Reserved

Reserved. Do not access.

IDFS

Ignore FS Detection

This bit controls whether to ignore the FS detection. When ignored, FS error will not cause a clock error.

Default value: 0

0: Regard FS detection

1: Ignore FS detection

IDBK

Ignore BCK Detection

This bit controls whether to ignore the BCK detection against LRCK. The BCK must be stable between 32FS

and 256FS inclusive or an error will be reported. When ignored, a BCK error will not cause a clock error.

Default value: 0

0: Regard BCK detection

1: Ignore BCK detection

IDSK

Ignore SCK Detection

This bit controls whether to ignore the SCK detection against LRCK. Only some certain SCK ratios within some

error margin are allowed. When ignored, an SCK error will not cause a clock error.

Default value: 0

0: Regard SCK detection

1: Ignore SCK detection

IDCH

Ignore Clock Halt Detection

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