PCM5142 datasheet(11/123 Pages) TI2

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tSCKH

System Clock

(SCK)

tSCKL

"L"

"H"

0.3*DVDD

0.7*DVDD

tSCY

PCM5141, PCM5142

www.ti.com

SLAS759B – AUGUST 2012 – REVISED JANUARY 2016

7.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DATA FORMAT (PCM MODE)

I2S, left-justified, right-justified, and

Audio data interface format

TDM

Audio data bit length

16, 20, 24, 32-bit acceptable

Audio data format

MSB first, twos-complement

Sampling frequency(1)

384

kHz

CLOCKS

64, 128, 192, 256, 384, 512, 768,

System clock frequency

1024, 1152, 1536, 2048, or 3072

fSCK, up to 50 Mhz

Clock divider uses fractional divide

6.7

MHz

D > 0, P=1

PLL input frequency (2)

Clock divider uses integer divide

MHz

D = 0, P=1

(1)

One sample time is defined as the reciprocal of the sampling frequency. 1 × tS = 1 / fS

(2)

With the appropriate P coefficient setting, the PLL accepts up to 50 MHz. This clock is then divided to meet the

≤ 20-MHz requirement.

See PLL Calculation.

Figure 1. Timing Requirements for SCK Input

Figure 2. PCM514x Serial Audio Timing - Slave

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Product Folder Links: PCM5141 PCM5142

PCM5142 Datasheet(PDF) 11 Page - Texas Instruments

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