PCM5142 datasheet(47/123 Pages) TI2

47 / 123 page

PCM5141, PCM5142

www.ti.com

SLAS759B – AUGUST 2012 – REVISED JANUARY 2016

Everything else should be a division of the incoming SCK. This is done by setting DAC CLK Source Mux (SDAC

in Figure 65) to use SCK as a source, rather than the output of the SCK/PLL Mux. Code examples for this are

available in SLASE12.

When the Auto Clock Configuration bit is set (Page 0/ Register 0x25), no additional clocks configuration is

required. However, when setting custom PLL values and so forth, the target output rates should match those

shown in the recommended PLL values of Table 132.

8.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)

The PCM514x requires a system clock to operate the digital interpolation filters and advanced segment DAC

modulators. The system clock is applied at the SCK input and supports up to 50 MHz. The PCM514x system-

clock detection circuit automatically senses the system-clock frequency. Common audio sampling frequencies in

the bands of 8 kHz, 16 kHz, (32 kHz - 44.1 kHz - 48 kHz), (88.2kHz - 96kHz), (176.4 kHz - 192 kHz), and 384

kHz with ±4% tolerance are supported. Values in the parentheses are grouped when detected, (for example,

88.2 kHZ and 96 kHz are detected as double rate, and 32 kHz, 44.1 kHz and 48 kHz are detected as single

rate.)

In the presence of a valid bit SCK, BCK and LRCK in software mode, the device will auto-configure the clock tree

and PLL to drive the miniDSP as required.

The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the

Negative Charge Pump (NCP) automatically. Table 32 shows examples of system clock frequencies for common

audio sampling rates.

SCK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are only supported in

software mode by configuring various PLL and clock-divider registers. This programmability allows the device to

become a clock master and drive the host serial port with LRCK and BCK, from a non-audio related clock (for

example, using 12 MHz to generate 44.1 kHz [LRCK] and 2.8224 MHz [BCK]).

Table 32. System Master Clock Inputs for Audio Related Clocks

SYSTEM CLOCK FREQUENCY (fSCK) (MHz)

SAMPLING

FREQUENCY

64 fS

128 fS

192 fS

256 fS

384 fS

512 fS

768 fS

1024 fS

1152 fS

1536 fS

2048 fS

3072 fS

8 kHz

–

(1)

1.024

(2)

1.536

(2)

2.048

3.072

4.096

6.144

8.192

9.216

12.288

16.384

24.576

16 kHz

–

(1)

2.048

(2)

3.072

(2)

4.096

6.144

8.192

12.288

16.384

18.432

24.576

36.864

49.152

32 kHz

–

(1)

4.096

(2)

6.144

(2)

8.192

12.288

16.384

24.576

32.768

36.864

49.152

–

(1)

–

(1)

44.1 kHz

–

(1)

5.6488

(2)

8.4672

(2)

11.2896

16.9344

22.5792

33.8688

45.1584

–

(1)

–

(1)

–

(1)

–

(1)

48 kHz

–

(1)

6.144

(2)

9.216

(2)

12.288

18.432

24.576

36.864

49.152

–

(1)

–

(1)

–

(1)

–

(1)

88.2 kHz

–

(1)

11.2896

(2)

16.9344

22.5792

33.8688

45.1584

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

96 kHz

–

(1)

12.288

(2)

18.432

24.576

36.864

49.152

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

176.4 kHz

–

(1)

22.579

33.8688

45.1584

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

192 kHz

–

(1)

24.576

36.864

49.152

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

384 kHz

24.576

49.152

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

–

(1)

This system clock rate is not supported for the given sampling frequency.

(2)

This system clock rate is supported by PLL mode.

See Timing Requirements: PCM Audio Data for clock timing requirements.

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