THS4521 datasheet(27/66 Pages) TI2

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Rf1

402

Rg1

191

Rg2

221

THS4541

Rf2

402

Rth

27.3

100 nF

Vcc

Vocm

Vcc

FDA

Vcc

Vs1

5 V

Vocm

Vcm

2.5 V

Figure 7-8. Input Swing Analysis Circuit from Figure 7-1 With Thevenized Source

For this ac-coupled input analysis, the nominal dc input Vicm is simply the output Vocm (2.5 V in this example

design). Then, considering the lower side of the feedback networks, any desired maximum output differential

VPP generates a known ac VPP at the junction of Rg2 and Rf2. For instance, if the design intends a maximum

4-VPP differential output, each FDA output pin is ±1 V around the Vocm (= 2.5 V), and then back to the Vicm,

which produces a ±1 V × 221 / (221 + 402) = ±0.355 V around the dc setting of Vocm. This simple approach to

assessing the input Vicm range for a single-ended to differential design can be applied to any design using an

FDA by reducing the input side circuits to a divider to either the signal source and ground or voltage reference on

the nonsignal input side.

7.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances

The THS4541 offers a trimmed input offset voltage and extremely low offset drift over the full –40°C to +125°C

operating range. This offset voltage combines with several other error contribution terms to produce an initial

25°C differential offset error band, and then a drift over temperature. For each error term, a gain must be

assigned to that term. For this analysis, only DC-coupled signal paths are considered. One new source of output

error (versus typical op amp analysis) arises from the effect that mismatched resistor values and ratios can have

on the two sides of the FDA. Any common-mode voltage or drift creates a differential output error through the

slight mismatches arising from the external feedback and gain-setting resistor tolerances, and the approximation

to standard value.

The error terms (25°C and drift), along with the gain to the output differential voltage, include:

• Input offset voltage—this voltage has a gain equal to the noise gain or 1 + Rf / Rg, where Rg is the total DC

impedance from the input pins back to the source, or a DC reference (typically ground).

• Input offset current—this current has a gain to the differential output through the average feedback resistor

value.

The remaining terms arise from an assumed range on both the absolute feedback resistor mismatch and the

mismatch in the divider ratio on each side of the FDA. The first of these resistor mismatch terms is the input

bias current creating a differential output offset because of Rf mismatch. For simplicity, the upper Rf and Rg

values are called Rf1 and Rg1 with a ratio of Rf1 / Rg1 ≡ G1. The lower elements are defined as Rf2 and

Rg2 with a ratio of Rf2 / Rg2 ≡ G2. To compute worst-case contributions, a maximum variation in the design

resistor tolerance is used in the absolute and ratio mismatches. For instance, ±1% tolerance resistors are

assumed, giving a worst-case G1 that is 2% higher than nominal and a G2 that is 2% lower than nominal,

with a worst-case Rf value mismatch of 2% as well. For matched impedance designs with Rt and Rg1 on

a single-ended to differential stage, the standard value approximation imposes a fixed mismatch in the initial

feedback ratios with the resistor tolerance adding a mismatch to this initial ratio mismatch. Define the selected

external resistor tolerance as ±T (so for 1% tolerance resistors, T = 0.01).

• Total gain for bias current error is ±2 × T × Rfnom

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THS4541

SLOS375B – AUGUST 2014 – REVISED FEBRUARY 2024

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