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ESP32-P4 Datasheet(PDF) 67 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. |
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ESP32-P4 Datasheet(HTML) 67 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. |
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67 / 93 page ![]() 4 Functional Description • 7-bit addressing • Adjustable transmission rate • Communication in the sleep modes supported by the Low-Power CPU • Dual master operation mode Pin Assignment The analog I2C interface connects internal analog components without requiring allocating IO pins. 4.2.2.5 I3C Controller ESP32-P4 includes one I3C master interface. Feature List The I3C master interface supports the following features: • Compliant with I3C protocol • Compatible with I2C mode (FM, FM+) • SDR mode • Dynamic address allocation • In-Band interrupts • DMA transfer Pin Assignment For I3C master interface, the pins for clock and data signals are multiplexed with GPIO32–GPIO33 via the GPIO matrix. Other signals can be routed to any GPIOs via the GPIO matrix. 4.2.2.6 I2S Controller (I2S) ESP32-P4 has three built-in I2S interfaces, which provide flexible communication interfaces for streaming digital data in multimedia applications, especially digital audio applications. Feature List • Master mode and slave mode • Full-duplex and half-duplex communications • Separate TX and RX units that can work independently or simultaneously • A variety of audio standards supported: – TDM Philips standard – TDM MSB alignment standard – TDM PCM standard Espressif Systems 67 Submit Documentation Feedback ESP32-P4 Series Datasheet v0.5 |
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