ESP32-P4 datasheet(70/93 Pages) ESPRESSIF

70 / 93 page

4 Functional Description

• USB 2.0 specification, OTG Revision 1.3 and OTG Revision 2.0 specifications

• High-Speed, Full-Speed, and Low-Speed data rates

• As a host and a device in High-Speed mode and Full-Speed mode

• Dynamic FIFO (DFIFO) sizing, each device EP/host channel can dynamically allocate a maximum of 4 KB

FIFO.

• Up to 8 non-periodic transactions and 16 periodic transactions per microframe

• Multiple modes of memory access

– Scatter/Gather DMA mode

– Buffer DMA mode

– Slave Mode

• Integrated UTMI High-Speed transceiver

Device Mode Features

• Endpoint 0 always present, bi-directional, consisting of EP0 IN and EP0 OUT

• 15 additional endpoints 1–15, configurable as IN or OUT

• Maximum of eight IN endpoints concurrently active at any time, including EP0 IN

• All OUT endpoints share a single RX FIFO

• Each IN endpoint has a dedicated TX FIFO

Host Mode Features

• 16 host channels

• RX FIFO: shared by all periodic and non-periodic transactions

• Two TX FIFO:

– One shared by all non-periodic transactions

– One shared by all periodic transactions

• All of the above FIFOs share a 4 KB RAM.

• The size of each FIFO is configurable, with a maximum of 4 KB.

Pin Assignment

The pins connected to USB2 OTG PHY DM (USB_D-) and USB2 OTG PHY DP (USB_D+) signals of USB 2.0

High-Speed OTG are dedicated pin49 and pin50. Other signals can be routed to any GPIOs via the GPIO

matrix.

4.2.2.10 USB 2.0 Full-Speed OTG

The ESP32-P4 features a USB 2.0 Full-Speed On-The-Go peripheral (henceforth referred to as OTG_FS) along

with integrated transceivers. This OTG_FS conforms to USB 2.0 specification, OTG Revision 1.3, and OTG

Revision 2.0 specifications, OTG_FS can operate as either a USB Host or Device and supports 12 Mbit/s

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ESP32-P4 Series Datasheet v0.5

ESP32-P4 Datasheet(PDF) 70 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.