HD64F36049 datasheet(392/562 Pages) RENESAS

392 / 562 page

Section 18 I

2C Bus Interface 2 (IIC2)

Rev. 3.00 Mar. 15, 2006 Page 360 of 526

REJ09B0060-0300

18.4.3

Master Receive Operation

In master receive mode, the master device outputs the receive clock, receives data from the slave

device, and returns an acknowledge signal. For master receive mode operation timing, see figures

18.7 and 18.8. The reception procedure and operations in master receive mode are shown below.

1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master

transmit mode to master receive mode. Then, clear the TDRE bit to 0.

2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,

and data received, in synchronization with the internal clock. The master device outputs the

level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.

3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise

of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF

is cleared to 0.

4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th

receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is

fixed low until ICDRR is read.

5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.

This enables the issuance of the stop condition after the next reception.

6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition.

7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0.

8. The operation returns to the slave receive mode.

HD64F36049 Datasheet(PDF) 392 Page - Renesas Technology Corp