HD64F36049 datasheet(396/562 Pages) RENESAS

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Section 18 I

2C Bus Interface 2 (IIC2)

Rev. 3.00 Mar. 15, 2006 Page 364 of 526

REJ09B0060-0300

TDRE

Data n

TEND

ICDRS

ICDRR

TRS

ICDRT

SCL

(Master output)

SDA

(Master output)

SDA

(Slave output)

SCL

(Slave output)

Bit 7

Slave transmit mode

Slave receive

mode

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

[3] Clear TEND

[5] Clear TDRE

[4] Read ICDRR (dummy read)

after clearing TRS

User

processing

Figure 18.10 Slave Transmit Mode Operation Timing (2)

18.4.5

Slave Receive Operation

In slave receive mode, the master device outputs the transmit clock and transmit data, and the

slave device returns an acknowledge signal. For slave receive mode operation timing, see figures

18.11 and 18.12. The reception procedure and operations in slave receive mode are described

below.

1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0

bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive

mode, and wait until the slave address matches.

2. When the slave address matches in the first frame following detection of the start condition,

the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th

clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the

read data show the slave address and R/

W, it is not used.)

3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is

fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be

returned to the master device, is reflected to the next transmit frame.

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