HD64F36049 datasheet(399/562 Pages) RENESAS

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Section 18 I

2C Bus Interface 2 (IIC2)

Rev. 3.00 Mar. 15, 2006 Page 367 of 526

REJ09B0060-0300

SCL

TRS

Bit 0

Data 1

Data 2

Data 3

Data 2

Data 3

Bit 6

Bit 7

Bit 0

Bit 6

Bit 7

Bit 0

Bit 1

SDA

(Output)

TDRE

ICDRT

ICDRS

User

processing

[3] Write data

to ICDRT

[3] Write data

to ICDRT

[3] Write data

to ICDRT

[3] Write data

to ICDRT

[2] Set TRS

Figure 18.14 Transmit Mode Operation Timing

Receive Operation

In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when

MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, see figure

18.15. The reception procedure and operations in receive mode are described below.

1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial

setting)

2. When the transfer clock is output, set MST to 1 to start outputting the receive clock.

3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and

RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is

continually output. The continuous reception is performed by reading ICDRR every time

RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and

AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR.

4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is

fixed high after receiving the next byte data.

HD64F36049 Datasheet(PDF) 399 Page - Renesas Technology Corp

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