HD64F36049 datasheet(400/562 Pages) RENESAS

Part #	HD64F36049

Description	Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Tiny Series

PDF	562 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

400 / 562 page

Section 18 I

2C Bus Interface 2 (IIC2)

Rev. 3.00 Mar. 15, 2006 Page 368 of 526

REJ09B0060-0300

SCL

MST

TRS

RDRF

ICDRS

ICDRR

SDA

(Input)

Bit 0

Bit 6

Bit 7

Bit 0

Bit 6

Bit 7

Bit 0

Bit 1

User

processing

Data 1

Data 2

Data 3

[2] Set MST

(when outputting the clock)

[3] Read ICDRR

Figure 18.15 Receive Mode Operation Timing

18.4.7

Noise Canceller

The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched

internally. Figure 18.16 shows a block diagram of the noise canceller circuit.

The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA)

input signal is sampled on the system clock, but is not passed forward to the next circuit unless the

outputs of both latches agree. If they do not agree, the previous value is held.

March detector

Internal

SCL or SDA

signal

SCL or SDA

input signal

Sampling

clock

Sampling clock

System clock

period

Latch

Figure 18.16 Block Diagram of Noise Canceller

HD64F36049 Datasheet(PDF) 400 Page - Renesas Technology Corp

HD64F36049 Datasheet(HTML) 400 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL