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HD64F36049 Datasheet(PDF) 417 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 417 Page - Renesas Technology Corp |
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417 / 562 page ![]() Section 19 A/D Converter Rev. 3.00 Mar. 15, 2006 Page 385 of 526 REJ09B0060-0300 19.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (t D) has passed after the ADST bit is set to 1, then starts conversion. Figure 19.2 shows the A/D conversion timing. Table 19.3 shows the A/D conversion time. As indicated in figure 19.2, the A/D conversion time includes t D and the input sampling time. The length of t D varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 19.3. In scan mode, the values given in table 19.3 apply to the first conversion time. In the second and subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states (fixed) when CKS = 1. (1) (2) φ Address Write signal Input sampling timing ADF [Legend] (1): (2): t D: t SPL: t CONV: ADCSR write cycle ADCSR address A/D conversion start delay time Input sampling time A/D conversion time t CONV t SPL t D Figure 19.2 A/D Conversion Timing |
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