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HD64F36049 Datasheet(PDF) 418 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 418 Page - Renesas Technology Corp |
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418 / 562 page  Section 19 A/D Converter Rev. 3.00 Mar. 15, 2006 Page 386 of 526 REJ09B0060-0300 Table 19.3 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol Min. Typ. Max. Min. Typ. Max. A/D conversion start delay time t D 6 — 9 4 — 5 Input sampling time t SPL — 31 — — 15 — A/D conversion time t CONV 131 — 134 69 — 70 Note: All values represent the number of states. 19.4.4 External Trigger Input Timing A/D conversion can also be started by an external trigger input. When the TRGE bit in ADCR is set to 1, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG input pin sets the ADST bit in ADCSR to 1, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 19.3 shows the timing. φ ADTRG Internal trigger signal ADST A/D conversion Figure 19.3 External Trigger Input Timing |
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