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HD64F36049 Datasheet(PDF) 181 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 181 Page - Renesas Technology Corp |
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181 / 562 page ![]() Section 10 Realtime Clock (RTC) Rev. 3.00 Mar. 15, 2006 Page 149 of 526 REJ09B0060-0300 10.3.1 Second Data Register/Free Running Counter Data Register (RSECDR) RSECDR counts the BCD-coded second value. The setting range is decimal 00 to 59. It is an 8-bit read register used as a counter, when it operates as a free running counter. For more information on reading seconds, minutes, hours, and day-of-week, see section 10.4.3, Data Reading Procedure. Bit Bit Name Initial Value R/W Description 7 BSY — R RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 SC12 SC11 SC10 — — — R/W R/W R/W Counting Ten's Position of Seconds Counts on 0 to 5 for 60-second counting. 3 2 1 0 SC03 SC02 SC01 SC00 — — — — R/W R/W R/W R/W Counting One's Position of Seconds Counts on 0 to 9 once per second. When a carry is generated, 1 is added to the ten's position. |
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