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HD64F36049 Datasheet(PDF) 236 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 236 Page - Renesas Technology Corp |
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236 / 562 page ![]() Section 13 Timer W Rev. 3.00 Mar. 15, 2006 Page 204 of 526 REJ09B0060-0300 13.5 Operation Timing 13.5.1 TCNT Count Timing Figure 13.14 shows the TCNT count timing when the internal clock source is selected. Figure 13.15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock ( φ) cycles; shorter pulses will not be counted correctly. TCNT TCNT input clock Internal clock φ N N+1 N+2 Rising edge Figure 13.14 Count Timing for Internal Clock Source TCNT TCNT input clock External clock φ N N+1 N+2 Rising edge Rising edge Figure 13.15 Count Timing for External Clock Source |
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