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HD64F36049 Datasheet(PDF) 240 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 240 Page - Renesas Technology Corp |
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240 / 562 page  Section 13 Timer W Rev. 3.00 Mar. 15, 2006 Page 208 of 526 REJ09B0060-0300 13.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register. The compare match signal is generated in the last state in which the values match (when TCNT changes from the matching value to the next value). Therefore, when TCNT matches a general register, the compare match signal is generated only after the next TCNT clock pulse is input. Figure 13.21 shows the timing of the IMFA to IMFD flag setting at compare match. GRA to GRD TCNT TCNT input clock φ N N N+1 Compare match signal IMFA to IMFD IRRTW Figure 13.21 Timing of IMFA to IMFD Flag Setting at Compare Match |
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