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HD64F36049 Datasheet(PDF) 241 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 241 Page - Renesas Technology Corp |
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241 / 562 page  Section 13 Timer W Rev. 3.00 Mar. 15, 2006 Page 209 of 526 REJ09B0060-0300 13.5.7 Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 13.22 shows the timing of the IMFA to IMFD flag setting at input capture. GRA to GRD TCNT Input capture signal φ N N IMFA to IMFD IRRTW Figure 13.22 Timing of IMFA to IMFD Flag Setting at Input Capture 13.5.8 Timing of Status Flag Clearing When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 13.23 shows the status flag clearing timing. IMFA to IMFD Write signal Address φ TSRW address IRRTW TSRW write cycle T 1 T 2 Figure 13.23 Timing of Status Flag Clearing by CPU |
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