HD64F36049 datasheet(245/562 Pages) RENESAS

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Section 14 Timer Z

Rev. 3.00 Mar. 15, 2006 Page 213 of 526

REJ09B0060-0300

Section 14 Timer Z

The timer Z has a 16-bit timer with two channels. Figures 14.1, 14.2, and 14.3 show the block

diagrams of entire timer Z, its channel 0, and its channel 1, respectively. For details on the timer Z

functions, see table 14.1.

14.1

Features

• Capability to process up to eight inputs/outputs

• Eight general registers (GR): four registers for each channel

 Independently assignable output compare or input capture functions

• Selection of five counter clock sources: four internal clocks (φ, φ/2, φ/4, and φ/8) and an

external clock

• Seven selectable operating modes

 Output compare function

Selection of 0 output, 1 output, or toggle output

 Input capture function

Rising edge, falling edge, or both edges

 Synchronous operation

Timer counters_0 and _1 (TCNT_0 and TCNT_1) can be written simultaneously.

Simultaneous clearing by compare match or input capture is possible.

 PWM mode

Up to six-phase PWM output can be provided with desired duty ratio.

 Reset synchronous PWM mode

Three-phase PWM output for normal and counter phases

 Complementary PWM mode

Three-phase PWM output for non-overlapped normal and counter phases

The A/D conversion start trigger can be set for PWM cycles.

 Buffer operation

The input capture register can be consisted of double buffers.

The output compare register can automatically be modified.

• High-speed access by the internal 16-bit bus

 16-bit TCNT and GR registers can be accessed in high speed by a 16-bit bus interface

• Any initial timer output value can be set

• Output of the timer is disabled by external trigger

HD64F36049 Datasheet(PDF) 245 Page - Renesas Technology Corp