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HD64F36049 Datasheet(PDF) 248 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 248 Page - Renesas Technology Corp |
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248 / 562 page  Section 14 Timer Z Rev. 3.00 Mar. 15, 2006 Page 216 of 526 REJ09B0060-0300 ITMZ0 FTIOD0 FTIOC0 FTIOB0 FTIOA0 TCNT_0 : GRA_0, GRB_0: GRC_0, GRD_0 : TCR_0: TIORA_0: TIER_0: TSR_0: ITMZ0: Timer counter_0 (16 bits) General registers A_0, B_0, C_0, and D_0 (input capture/output compare registers: 16 bits × 4) Timer control register_0 (8 bits) Timer I/O control register A_0 (8 bits) TIORC_0: Timer I/O control register C_0 (8 bits) Timer interrupt enable register_0 (8 bits) POCR_0: PWM mode output level control register_0 (8 bits) Timer status register_0 (8 bits) Channel 0 interrupt [Legend] φ, φ/2, φ/4, φ/8 Clock select Control logic Module data bus Comparator Figure 14.2 Timer Z (Channel 0) Block Diagram |
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