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HD64F36049 Datasheet(PDF) 303 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 303 Page - Renesas Technology Corp |
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303 / 562 page  Section 14 Timer Z Rev. 3.00 Mar. 15, 2006 Page 271 of 526 REJ09B0060-0300 GRA N n TCNT Compare match signal Buffer transfer signal n n+1 GRC N φ Figure 14.39 Example of Compare Match Timing for Buffer Operation Figure 14.40 shows an operation example in which GRA has been designated as an input capture register, and buffer operation has been designated for GRA and GRC. Counter clearing by input capture B has been set for TCNT, and falling edges have been selected as the FIOCB pin input capture input edge. And both rising and falling edges have been selected as the FIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in GRA upon the occurrence of input capture A, the value previously stored in GRA is simultaneously transferred to GRC. The transfer timing is shown in figure 14.41. |
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