SH7101 datasheet(110/486 Pages) RENESAS

110 / 486 page

6. Interrupt Controller (INTC)

Rev.2.00 Sep. 27, 2007 Page 76 of 448

REJ09B0394-0200

When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC

during the period the IRQ pin is low level. Interrupt request signals are not sent to the INTC when

the IRQ pin becomes high level. Interrupt request levels can be confirmed by reading the IRQ

flags (IRQ0F to IRQ3F) of the IRQ status register (ISR).

When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the

INTC upon detecting a change on the IRQ pin from high to low level. The results of detection for

IRQ interrupt request are maintained until the interrupt request is accepted. It is possible to

confirm that IRQ interrupt requests have been detected by reading the IRQ flags (IRQ0F to

IRQ3F) of the IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request

detection results can be withdrawn.

In IRQ interrupt exception processing, the interrupt mask bits (I3 to I0) of the status register (SR)

are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block

diagram of this IRQ3 to IRQ0 interrupts.

IRQnS

IRQnES

ISR.IRQnF

IRQ pins

RESIRQn

Level

detection

Edge

detection

CPU interrupt

request

(Acceptance of IRQn interrupt/writing 0 after reading IRQnF = 1)

Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control

SH7101 Datasheet(PDF) 110 Page - Renesas Technology Corp