SH7101 datasheet(111/486 Pages) RENESAS

111 / 486 page

6. Interrupt Controller (INTC)

Rev.2.00 Sep. 27, 2007 Page 77 of 448

REJ09B0394-0200

6.4.2

On-Chip Peripheral Module Interrupts

On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral

modules.

As a different interrupt vector is assigned to each interrupt source, the exception service routine

does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be

assigned to individual on-chip peripheral modules in interrupt priority registers A, D to I (IPRA,

IPRD to IPRI). On-chip peripheral module interrupt exception processing sets the interrupt mask

level bits (I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral

module interrupt that was accepted.

6.5

Interrupt Exception Processing Vectors Table

Table 6.2 lists interrupt sources and their vector numbers, vector table address offsets and interrupt

priorities.

Each interrupt source is allocated a different vector number and vector table address offset. Vector

table addresses are calculated from the vector numbers and address offsets. In interrupt exception

processing, the exception service routine start address is fetched from the vector table indicated by

the vector table address. For the details of calculation of vector table address, see table 5.4,

Calculating Exception Processing Vector Table Addresses in the section 5 Exception Processing.

IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and

15 for each pin or module by setting interrupt priority registers A, D to I (IPRA, IPRD to IPRI).

However, the smaller vector number has interrupt source, the higher priority ranking is assigned

among two or more interrupt sources specified by the same IPR, and the priority ranking cannot be

changed. A power-on reset assigns priority level 0 to IRQ interrupts and on-chip peripheral

module interrupts. If the same priority level is assigned to two or more interrupt sources and

interrupts from those sources occur simultaneously, they are processed by the default priority

order indicated in table 6.2.

SH7101 Datasheet(PDF) 111 Page - Renesas Technology Corp