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SH7101 Datasheet(PDF) 238 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 238 Page - Renesas Technology Corp |
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238 / 486 page  8. Multi-Function Timer Pulse Unit (MTU) Rev.2.00 Sep. 27, 2007 Page 204 of 448 REJ09B0394-0200 8.7 Usage Notes 8.7.1 Module Standby Mode Setting MTU operation can be disabled or enabled using the module standby register. The initial setting is for MTU operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 17, Power-Down Modes. 8.7.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 8.69 shows the input clock conditions in phase counting mode. Overlap Phase differ- ence Phase differ- ence Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap Pulse width : 1.5 states or more : 2.5 states or more Figure 8.69 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode |
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