3886 datasheet(121/380 Pages) RENESAS

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3886 Group User’s Manual

APPLICATION

2.1 I/O port

2-4

Fig. 2.1.4 Structure of Port control register 1

Fig. 2.1.5 Structure of Port control register 2

Port control register 1

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

Port control register 1 (PCTL1) [Address 2E 16]

PWM1 enable bit

P00–P03 output structure

selection bit

0: PWM0 output disabled

1: PWM0 output enabled

P14–P17 output structure

selection bit

0: CMOS

1: N-channel open-drain

P04–P07 output structure

selection bit

P10–P13 output structure

selection bit

P30–P33 pull-up control bit

P34–P37 pull-up control bit

PWM0 enable bit

0: CMOS

1: N-channel open-drain

0: CMOS

1: N-channel open-drain

0: CMOS

1: N-channel open-drain

0: No pull-up

1: Pull-up

0: No pull-up

1: Pull-up

0: PWM1 output disabled

1: PWM1 output enabled

Port control register 2

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

Port control register 2 (PCTL2) [Address 2F 16]

Port output P42/P43 clear

function selection bit

P4 input level selection bit

(P4 2–P46)

0: Automatic set “01 16” to timer 1

and “FF 16” to prescaler 12

1: No automatic set

P8 function selection bit

0: CMOS level input

1: TTL level input

P7 input level selection bit

(P7 0–P75)

P4 output structure selection bit

(P4 2, P43, P44, P46)

INT2, INT3, INT4 interrupt

switch bit

Timer Y count source

selection bit

Oscillation stabilizing time set

after STP instruction released

bit

0: CMOS level input

1: TTL level input

0: CMOS

1: N-channel open-drain

0: Port P8/Port P8 direction

1: Port P4 input register/Port P7

input register

0: INT20, INT30, INT40 interrupt

1: INT21, INT31, INT41 interrupt

0: f(XIN)/16 (f(XCIN)/16 in low-

speed mode)

1: f(XCIN)

0: Only software clear

1: Software clear and output data

bus buffer 0 reading

(system bus side)

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