3886 datasheet(181/380 Pages) RENESAS

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2-64

3886 Group User’s Manual

APPLICATION

2.4 Serial I/O

The communication is performed according to the timing shown in Figure 2.4.33. In the slave unit,

when a synchronous clock is not input within a certain time (heading adjustment time), the next clock

input is processed as the beginning (heading) of a block.

When a clock is input again after one block (8 byte) is received, the clock is ignored.

Figure 2.4.34 shows relevant registers setting.

Fig. 2.4.33 Timing chart

Fig. 2.4.34 Relevant registers setting

Byte cycle

Block transfer term

Block transfer cycle

Interval between blocks

Processing for heading adjustment

Heading adjustment time

Master unit

Transmit enabled

SIO1CON

Serial I/O1 control register (Address : 1A16)

Synchronous clock : BRG/4

Transmit interrupt source :

Transmit shift operating completion

Receive enabled

Clock synchronous serial I/O

110

Serial I/O1 enabled

BRG count source : f(XIN)

SRDY1

output disabled

Not affected by external clock

Transmit enabled

SIO1CON

Serial I/O1 control register (Address : 1A16)

Not use the serial I/O1 transmit interrupt

Receive enabled

Clock synchronous serial I/O

Slave unit

Serial I/O1 enabled

Synchronous clock : External clock

UARTCON

UART control register (Address : 1B16)

P45/TXD pin : CMOS output

Both of units

b7b0

BRG

b7b0

Baud rate generator (Address : 1C16)

Set “division ratio – 1”.

SRDY1

output disabled

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