3886 datasheet(201/380 Pages) RENESAS

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3886 Group User’s Manual

APPLICATION

2.5 Multi-master I2C-BUS interface

2.5.4 Communication format

Figure 2.5.14 shows an I2C-BUS communication format example.

The I2C-BUS consists of the following:

•START condition to indicate communication start

•Slave address and data to specify each device

•ACK to indicate acknowledgment of address and data

•STOP condition to indicate communication completion.

Fig. 2.5.14 I2C-BUS communication format example

(1)

START condition

When communication starts, the master device outputs the START condition to the slave device. The

I2C-BUS defines that data can be changed when a clock line is “L”. Accordingly, data change when

a clock line is “H” is treated as STOP or START condition.

The data line change from “H” to “L” when a clock line is “H” is START condition.

(2)

STOP condition

Just as in START condition, the data line change from “L” to “H” when a clock line is “H” is STOP

condition.

The term from START condition to STOP condition is called “Bus busy”. The master device is

inhibited from starting data transfer during that term.

The Bus busy status can be judged by using the BB flag of I2C status register (bit 5 of address

001416).

(3)

Slave address

The slave address is transmitted after START condition. This address consists of 7 bits and the 7-

th bit functions as the read/write (R/W) bit which indicates a data transmission method. The slave

devices connected with the same I2C-BUS must have their addresses, individually. It is because that

address is defined for the master to specify the transmitted/received slave device.

The read/write (R/W) bit indicates a data transmission direction; “L” means write from the master to

the slave, and “H” means read in.

(4)

Data

The data has an 8-bit length. There are two cases depending on the read/write (R/W) bit of a slave

address; one is from the master to the slave and the other is from the slave to the master.

R/W A

SCL

SDA

StartACK

ACK

Stop

Bus busy term

Slave address

7 bits

Data

8 bits

Data

8 bits

Addresses 0 to 6Data 0 to 7

Data 0 to 7

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