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7480 Datasheet(PDF) 237 Page - Renesas Technology Corp

Part # 7480
Description  8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7470 SERIES
PDF  337 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7480 Datasheet(HTML) 237 Page - Renesas Technology Corp

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7480 Group and 7481 Group User's Manual
2-22
APPLICATIONS
2.3 Serial I/O
2.3.2 Application Example of Clock Asynchronous Serial I/O (UART) Reception
Processing of Received Data Bytes as a Packet
POINT: RAM area is secured by adding the several bytes to the maximum number of bytes necessary
for data processing, and the received data is stored in increasing order of address in the
interrupt service routine. If the data overflows the RAM area, the overflow data is stored at
the start address of the RAM.
When the received data whose byte number satisfies the requirement of data processing is
stored completely in the buffer area, the data processing is performed in the main routine.
As a result, the received data can be stored without losing any bits of data in process even
when the subsequent received data is stored completely during the data processing.
SPECIFICATIONS:
Clock: f(XIN) = 7.9872 MHz
UART reception
• Baud rate : 9600 bps
• Synchronous clock : f(XIN) is divided into 9.6 kHz
• Communication format: 1ST-8DATA-1SP
Processing received data as a packet
The head data of every packet consists of the code characteristic for the head
data and the code indicating the number of bytes of the packet.
Figure 2.3.5 shows a connection example.
Figure 2.3.6 shows the setting example of the
synchronous clock.
Figure 2.3.7 shows a communication format.
Figure 2.3.8 shows a control procedure example
of serial I/O receive.
Figure 2.3.7 Communication Format
Figure 2.3.6 Setting Example of Synchronous Clock
f(XIN) = 7.9872 MHz
BRG count source
selection bit
Baud rate
generator
Synchronous clock
9.6 kHz
Baud rate : 9600bps
1/4
1/4
1/13
1/16
Clock
generator
‘0’
‘1’
BRG output
Figure 2.3.5 Connection Example
TxD
P14/RxD
7480 Group
7481 Group
(Receiver)
Microcomputer
(Transmitter)
D0
D1
D6
D7
ST
SP
LSB
MSB
Transmit data (1ST-8DATA-1SP)
1st byte
(n – 1)th byte
1 packet (N bytes)
Head data
∗
ST:
Di:
SP:
N:
Start bit
Data bit (i = 0 to 7)
Stop bit
The number of bytes of the packet
: Consists of the code characteristic for the head data
and the code indicating the number of bytes of
the packet.
∗



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