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7480 Datasheet(PDF) 239 Page - Renesas Technology Corp

Part # 7480
Description  8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7470 SERIES
PDF  337 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7480 Datasheet(HTML) 239 Page - Renesas Technology Corp

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7480 Group and 7481 Group User's Manual
2-24
APPLICATIONS
2.3 Serial I/O
2.3.3 Application Example of Bus Arbitration Interrupt
LAN Communications in Contention Bus System
POINT: In LAN communications with the contention bus system, the malfunction of transmission due
to bus collision is detected with a bus arbitration interrupt.
SPECIFICATIONS:
Clock: f(XIN) = 7.9872 MHz
LAN communication format: Simplified SAE J1850 (PWM system)
The CNTR0 pin is connected to the RxD pin, and SOF is detected with the
rising edge of a CNTR0 pin input
Data is transmitted and received by clock synchronous serial I/O communications.
• Baud rate: 41600 bps
• Synchronous clock: f(XIN) is divided into 41.6 kHz
• Bus collision detected
The HIGH level has priority on LAN communication line at bus collision
Figure 2.3.9 shows a connection example.
Figure 2.3.10 shows a setting example of the synchronous clock.
Figure 2.3.11 shows a communication format example of simple SAE J1850.
Figure 2.3.12 shows a communication timing example.
Figures 2.3.13 and 2.3.14 show control procedure examples.
P14/RxD
P15/TxD
7480 Group
7481 Group
P40/CNTR0
IN
OUT
BUS +
BUS –
Driver
LAN communication Line (+)
LAN communication Line (–)
Unit A
Unit B
Unit C
Unit D
Unit A
TxD pin output
Unit B
TxD pin output
LAN communication line
(RxD pin input)
• Conflicts between unit A and unit B
H
L
H
L
H
L
Bus collision
detected in unit B
Figure 2.3.9 Connection Example
Baud rate : 41600bps
f(XIN)=7.9872MHz
1/4
1/4
1/3
1/4
BRG count source
selection bit
Baud rate
generator
Synchronous clock
41.6 kHz
Clock
generator
‘0’
‘1’
BRG output
Figure 2.3.10 Setting Example of Synchronous Clock



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