7480 datasheet(242/337 Pages) RENESAS

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7480 Group and 7481 Group User's Manual

2-27

APPLICATIONS

2.3 Serial I/O

Figure 2.3.13 Control Procedure Example (1) of LAN Communications

Initialize

RESET(Note 1)

0 0

During transmitting

SEI

Serial I/O transmit interrupt enable bit

← 1

Serial I/O receive interrupt enable bit

← 1

CNTR0 interrupt enable bit

← 1

CLI

Transmit service routine

END

Receive service routine

END

Receive service routine

During receiving

Set serial I/O control register (Note 3)

SIOCON (Address 00E216)

BRG count source: f(XIN)/16

Synchronous clock:

BRG output divided by 4

Baud rate generator

← 0216 (Note 2)

Transmission requested ?

Transmit interrupt source:

Transmit enabled

Receive enabled

Clock synchronous serial I/O

Serial I/O enabled

SRDY output disabled

Transmission buffer register is empty.

Processing

Port P40 (alternative function of CNTR0 pin) is set to input.

Processing

During transmission or reception ?

CNTR0 edge selection bit

← 1

(Rising edge active)

Bus collision detection enable bit

← 1

When transmit is started

• Transmit data generated

(1 byte represented by 3 bytes)

• Bus arbitration interrupt request bit

← 0

• Bus arbitration interrupt enable bit

← 1

• CNTR0 interrupt enable bit

← 0

• SOF transmission (writing to transmit buffer register)

When EOD is output, waiting time is generated

(Note 3)

After EOD waiting time elapses, RSP code is received

(writing dummy data to transmit buffer register)

After receiving RSP code, EOF and IFS are output and

waiting time is generated (Note 3)

After EOF/IFS waiting time elapses

(when transmit completed)

• Bus arbitration interrupt enable bit

← 0

• CNTR0 interrupt request bit

← 0

• CNTR0 interrupt enable bit

← 1

Notes 1: State after system is released from reset

• Bus arbitration interrupt enable bit = 0

2: 0216 = 3–1

3: Waiting time is generated by timer 1.

4: Write ‘0016’ as dummy data to transmit buffer register.

After SOF receive is completed

• CNTR0 interrupt enable bit

← 0

When priority code to CRC code, and RSP code

are received

3-byte receive data is converted to 1-byte data.

Receive processing is completed after recognizing

that received target ID is not self ID.

When EOD is detected, EOD waiting time is

generated (Note 3)

When the correct reception is checked by CRC code

after EOD waiting time elapses, RSP code is

transmitted (writing to transmit buffer register)

After transmitting RSP code, EOF and IFS

waiting time is generated (Note 3)

After EOF/IFS wait time elapses

(when receive completed)

• CNTR0 interrupt request bit

← 0

• CNTR0 interrupt enable bit

← 1

Serial I/O transmit interrupt request bit

← 0

Serial I/O receive interrupt request bit

← 0

CNTR0 interrupt request bit

← 0

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