7480 datasheet(274/337 Pages) RENESAS

274 / 337 page

3-9

3.1 Control Registers

APPENDICES

7480 Group and 7481 Group User's Manual

Figure 3.1.12 Serial I/O Control Register

Figure 3.1.13 UART Control Register

Serial I/O control register

b4 b3 b2 b1 b0

Name

Function

At reset

Serial I/O control register (SIOCON) [Address 00E216]

BRG count source

selection bit (CSS)

0 : f(XIN)/4

1 : f(XIN)/16

Serial I/O synchronous

clock selection bit (SCS)

when clock synchronous serial I/O is selected

0 : BRG output/4

1 : External clock input

when UART is selected

0 : BRG output/16

1 : External clock input/16

Transmit interrupt source

selection bit (TIC)

Transmit enable bit

(TE)

Receive enable bit

(RE)

Serial I/O mode selection bit

(SIOM)

Serial I/O enable bit

(SIOE)

0 : Interrupt occurs when transmit

buffer is empty.

1 : Interrupt occurs when transmit shift

operation is completed.

0 : Transmit disabled

1 : Transmit enabled

0 : Receive disabled

1 : Receive enabled

0 : Asynchronous serial I/O (UART)

1 : Clock synchronous serial I/O

0 : Serial I/O disabled

1 : Serial I/O enabled

SRDY output enable bit

(SRDY)

0 : P17 pin

1 : SRDY output pin

UART control register

b4 b3 b2 b1 b0

Name

Function

At reset

UART control register (UARTCON) [Address 00E316]

Character length selection bit

(CHAS)

Parity enable bit

(PARE)

Parity selection bit

(PARS)

Stop bit length selection bit

(STPS)

0 : 8 bits

1 : 7 bits

0 : Parity disabled

1 : Parity enabled

0 : Even parity

1 : Odd parity

0 : 1 stop bit

1 : 2 stop bits

These bits are fixed to ‘1’.

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