7480 datasheet(273/337 Pages) RENESAS

273 / 337 page

3-8

3.1 Control Registers

APPENDICES

7480 Group and 7481 Group User's Manual

Figure 3.1.10 Transmit/Receive Buffer Register

Figure 3.1.11 Serial I/O Status Register

Serial I/O status register

b4 b3 b2 b1 b0

Name

Function

At reset

Serial I/O status register (SIOSTS) [Address 00E116]

Transmit buffer empty flag

(TBE)

Receive buffer full flag

(RBF)

Transmit shift completion

flag (TSC)

Overrun error flag

(OE)

Parity error flag

(PE)

Framing error flag

(FE)

Summing error flag

(SE)

0 : Buffer full

1 : Buffer empty

0 : Buffer empty

1 : Buffer full

0 : Transmit shift in progress

1 : Transmit shift completed

0 : No error

1 : Overrun error

0 : No error

1 : Parity error

0 : No error

1 : Framing error

0 : OE U PE U FE=0

1 : OE U PE U FE=1

This bit is fixed to ‘1’.

Note: b4 and b5 are valid only in UART

Transmit/Receive buffer register

b4 b3 b2 b1 b0

Function

At reset

Undefined

Transmit/Receive buffer register (TB/RB) [Address 00E016]

In transmission:

Transmit data is transferred to the transmit shift register

by writing transmit data.

In reception:

When data is stored completely in the receive shift

Note: In transmission, this register is a write-only register.

Undefined

In reception, this register is a read-only register.

Note

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