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7480 Datasheet(PDF) 282 Page - Renesas Technology Corp |
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7480 Datasheet(HTML) 282 Page - Renesas Technology Corp |
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282 / 337 page  3-17 3.1 Control Registers APPENDICES 7480 Group and 7481 Group User's Manual Figure 3.1.26 CPU Mode Register CPU mode register b5 b6 b7 b4 b3 b2 b1 b0 b Name Function At reset 1 2 3 4 5 6 7 0 0 0 0 0 Undefined 0 Undefined CPU mode register (CPUM) [Address 00FB16] Fix these bits to ‘0’. Stack page selection bit (Note) 0 : Zero page 1 : 1 page Watchdog timer L count source selection bit 0 : f(XIN)/8 1 : f(XIN)/16 Clock division ratio selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (medium-speed mode) Not implemented. Writing to this bit is disabled. This bit is undefined at reading. Not implemented. Writing to this bit is disabled. This bit is undefined at reading. Note: In the products whose RAM size is 192 bytes or less, set this bit to ‘0’. 0 0 Not implemented. Writing to this bit is disabled. This bit is undefined at reading. Undefined RW O O 0 O Undefined Undefined Undefined × × × O0 OO OO |
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