7480 datasheet(283/337 Pages) RENESAS

283 / 337 page

3-18

3.1 Control Registers

APPENDICES

7480 Group and 7481 Group User's Manual

Figure 3.1.27 Interrupt Request Register 1

Figure 3.1.28 Interrupt Request Register 2

Interrupt request register 1

b4 b3 b2 b1 b0

Name

Function

At reset

Interrupt request register 1 (IREQ1) [Address 00FC16]

Timer X interrupt request bit

Timer Y interrupt request bit

Timer 1 interrupt request bit

Timer 2 interrupt request bit

Serial I/O receive

interrupt request bit

Serial I/O transmit

interrupt request bit

Bus arbitration interrupt

request bit

A-D conversion completion

interrupt request bit

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

∗: The bit can be set to ‘0’ by software, but cannot be set to ‘1’.

∗

Interrupt request register 2

b4 b3 b2 b1 b0

Name

Function

At reset

Undefined

Interrupt request register 2 (IREQ2) [Address 00FD16]

INT0 interrupt request bit

INT1 interrupt request bit

CNTR0 interrupt request bit

CNTR1 interrupt request bit

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

0 : No interrupt request

1 : Interrupt request

∗: The bit can be set to ‘0’ by software, but cannot be set to ‘1’.

Not implemented.

Writing to these bits is disabled.

These bits are undefined at reading.

Undefined

∗

Undefined

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