7480 datasheet(284/337 Pages) RENESAS

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3-19

3.1 Control Registers

APPENDICES

7480 Group and 7481 Group User's Manual

Figure 3.1.29 Interrupt Control Register 1

Figure 3.1.30 Interrupt Control Register 2

Interrupt control register 2

b4 b3 b2 b1 b0

Name

Function

At reset

Undefined

Interrupt control register 2 (ICON2) [Address 00FF16]

INT0 interrupt enable bit

INT1 interrupt enable bit

CNTR0 interrupt enable bit

CNTR1 interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

Not implemented.

Writing to these bits are disabled.

These bits are undefined at reading.

Undefined

Interrupt control register 1

b4 b3 b2 b1 b0

Name

Function

At reset

Interrupt control register 1 (ICON1) [Address 00FE16]

Timer X interrupt enable bit

Timer Y interrupt enable bit

Timer 1 interrupt enable bit

Timer 2 interrupt enable bit

Serial I/O receive

interrupt enable bit

Serial I/O transmit

interrupt enable bit

Bus arbitration interrupt

enable bit

A-D conversion completion

interrupt enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

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