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ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.02/November 2005 © Semtech Corp.

Page 34

www.semtech.com

ACS8530 SETS

The frequency generated from the T4 output APLL block is

four times its input frequency i.e. 311.04 MHz when used

with a 77.76 MHz input. The T4 output APLL is

subsequently divided by 2, 4, 8, 12, 16, 48 and 64 and

these are available at the TO1-TO7 outputs.

The TO8 and TO9 outputs are driven from either the T4 or

the T0 path. The TO10 and TO11 outputs are always

generated from the T0 path. Reg. 7A Bit 7 selects whether

the source of the 2 kHz and 8 kHz outputs available from

TO1-TO7 is derived from either the T0 or the T4 paths.

Output Frequency Configuration Steps

The output frequency selection is performed in the

following steps:

1. Does the application require the use of the T4 path as

an independent PLL path or not. If not, then the T4

path can be utilized to produce extra frequencies

locked to the T0 path.

2. Refer to Table 14, Frequency Divider Look-up, to

choose a set of output frequencies- one for each path,

T4 and T0. Only one set of frequencies can be

generated simultaneously from each path.

3. Refer to the Table 14 to determine the required APLL

frequency to support the frequency set.

4. Refer to Table 15, T0 APLL Frequencies, and

Table 16, T4 APLL Frequencies, to determine what

mode the T0 and T4 paths need to be configured in,

considering the output jitter level.

5. Refer to Table 17, TO1 - TO7 output Frequency

Selection, and the column headings in Table 14,

Frequency Divider Look-up, to select the appropriate

frequency from either of the APLLs on each output as

required.

Note...1.544 MHz/2.048 MHz are shown for SONET/SDH respectively. Pin SONSDHB controls default, when High SONET is default

Table 12 Output Reference Source Selection Table

Port

Name

Output Port

Technology

Frequencies Supported

T01

TTL/CMOS

Frequency selection as per Table 13 and Table 17

T02

TTL/CMOS

T03

TTL/CMOS

T04

TTL/CMOS

T05

TTL/CMOS

T06

LVDS/PECL

(LVDS default)

T07

PECL/LVDS

(PECL default)

T08

AMI

64/8 kHz (composite clock, 64 kHz + 8 kHz), fixed frequency.

T09

TTL/CMOS

Fixed frequency, either 1.544 MHz or 2.048 MHz.

T010

TTL/CMOS

FrSync, 8 kHz programmable pulse width and polarity, see Reg. 7A.

T011

TTL/CMOS

MFrSync, 2 kHz programmable pulse width and polarity, see Reg. 7A.

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