ACS8530 datasheet(67/152 Pages) SEMTECH

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ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.02/November 2005 © Semtech Corp.

Page 67

www.semtech.com

ACS8530 SETS

Address (hex):

[7:0]

Description

(RO) Bits [7:0] of the current DPLL

frequency.

Default Value

0000 0000

Bit 7Bit 6

Bit 5Bit 4

Bit 3

Bit 2Bit 1Bit 0

Bits [7:0] of sts_current_DPLL_frequency

Bit No.

Description

Bit Value

Value Description

[7:0]

Bits [7:0] of sts_current_DPLL_frequency

*When Bit 4 (T4_T0_select) of Reg. 4B

(cnfg_registers_source_select) = 0 the frequency

for the T0 path is reported.

When this Bit 4 = 1 the frequency for the T4 path is

reported.

See register description of

sts_current_DPLL_frequency at Reg. 0D.

Address (hex):

[15:8]

Description

(RO) Bits [15:8] of the current

DPLL frequency.

Default Value

0000 0000

Bit 7Bit 6

Bit 5Bit 4

Bit 3

Bit 2Bit 1Bit 0

sts_current_DPLL_frequency[15:8]

Bit No.

Description

Bit Value

Value Description

[7:0]

sts_current_DPLL_frequency[15:8]

This value in this register is combined with the value

in Reg. 0C and Reg. 07 to represent the current

frequency offset of the DPLL.

*When Bit 4 (T4_T0_select) of Reg. 4B

(cnfg_registers_source_select) = 0 the frequency

for the T0 path is reported.

When this Bit 4 = 1 the frequency for the T4 path is

reported.

In order to calculate the ppm offset of the DPLL with

respect to the crystal oscillator frequency, the value

in Reg. 07, Reg. 0D and Reg. 0C need to be

concatenated. This value is a 2’s complement

signed integer. The value multiplied by

0.0003068 dec will give the value in ppm offset

with respect to the XO frequency, allowing for any

crystal calibration that has been performed, via

cnfg_nominal_frequency, Reg. 3C and 3D. The

value is actually the DPLL integral path value so it

can be viewed as an average frequency, where the

rate of change is related to the DPLL bandwidth. If

bit 3 of Reg. 3B is High then this value will freeze if

the DPLL has been pulled to its min or max

frequency.

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