ACS8530 datasheet(40/152 Pages) SEMTECH

40 / 152 page

ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.02/November 2005 © Semtech Corp.

Page 40

www.semtech.com

ACS8530 SETS

Table 15 T0 APLL Frequencies

T0 APLL Frequency

T0 Mode

T0 DPLL Frequency Control Register Bits

Reg. 65 Bits[2:0]

Output Jitter Level

ns (p-p)

311.04

Normal (digital feedback)

000

<0.5

311.04 MHz

Normal (analog feedback)

001

<0.5

98.304 MHz

12E1 (digital feedback)

010

131.072 MHz

16E1 (digital feedback)

011

148.224 MHz

24DS1 (digital feedback)

100

98.816 MHz

16DS1 (digital feedback)

101

Do not use

110

Do not use

111

Table 16 T4 APLL Frequencies

T4 APLL

Frequency

T4 Mode

T4 Forward DFS

Frequency

(MHz)

T4 DPLL Frequency

Control Register Bits

Reg. 64 Bits [2:0]

T4 APLL for T0

Enable Register Bit

Reg. 65 Bit 6

T0 Frequency to T4

APLL Register Bits

Reg. 65 Bits [5:4]

Output Jitter Level

ns (p-p)

311.04 MHz

Squelched

77.76

000

<0.5

311.04 MHz

Normal

77.76

001

<0.5

98.304 MHz

12E1

24.576

010

<0.5

131.072 MHz

16E1

32.768

011

<0.5

148.224 MHz

24DS1

37.056

(2*18.528)

100

<0.5

98.816 MHz

16DS1

24.704

101

<0.5

274.944 MHz

68.736

(2*34.368)

110

<0.5

178.944 MHz

DS3

44.736

111

<0.5

98.304 MHz

T0-12E1

XXX

131.072 MHz

T0-16E1

XXX

148.224 MHz

T0-24DS1

XXX

98.816 MHz

T0-16DS1

XXX

ACS8530 Datasheet(PDF) 40 Page - Semtech Corporation

ACS8530 Datasheet(HTML) 40 Page - Semtech Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL