ACS8530 datasheet(33/152 Pages) SEMTECH

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ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.02/November 2005 © Semtech Corp.

Page 33

www.semtech.com

ACS8530 SETS

Figure 11 PLL Block Diagram

However, when the input to the T0 APLL is taken from the

T0 LF output DFS block, the input to that block comes

directly from the T0 77M output DFS block so that a “loop”

is not created.

The T0 output APLL is for multiplying and filtering. The

input to the T0 output APLL can be either 77.76 MHz from

the T0 77M output DFS block or an alternative frequency

from the T0 LF output DFS block (offering 77.76 MHz,

12E1, 16E1, 24DS1 or 16DS1). The frequency from the

T0 output APLL is four times its input frequency i.e.

311.04 MHz when used with a 77.76 MHz input. The T0

output APLL is subsequently divided by 1, 2, 4, 6, 8, 12,

16 and 48 and these are available at the TO1-TO7

outputs.

T4 DPLL & APLL

The T4 path is much simpler than the T0 path. This path

offers no Phase Build-out or phase offset. The T4 input

can be used to either lock to a reference clock input

independent of the T0 path, or lock to the T0 path. Unlike

the T0 path, the T4 forward DFS block does not always

generate 77.76 MHz. The possible frequencies are listed

in the table. Similar to the T0 path, the output of the T4

forward DFS block is generated using DFS clocked by the

204.8 MHz system clock and will have an inherent jitter of

4.9 ns.

The T4 feedback DFS also has the facility to be able to use

the post T4 APLL (jitter-filtered) clock to generate the

feedback locking frequency. Again, this will give the

maximum performance by using a low jitter feedback.

The T4 output APLL block is also for multiplying and

filtering. The input to the T4 output APLL can come either

from the T4 forward DFS block or from the T0 path. The

input to the T4 output APLL can be programmed to be one

of the following:

(a) Output from the T4 forward DFS block (12E1, 24DS1,

16E1, 16DS1, E3, DS3, OC-N),

(b) 12E1 from T0,

(d) 24DS1 from T0,

(e) 16DS1 from T0.

PFD and

Loop Filter

Forward

DFS

Feedback

DFS

F8530D_017BLOCKDIA_04

TO8 /TO9

TO1 to TO7

PFD and

Loop Filter

Feedback

DFS

77M

Forward

DFS

77M

Output

DFS

Output

DFS

Output

APLL

Output

Dividers

Output

APLL

Feedback

APLL

Output

Dividers

T4 DPLL

T0 DPLL

Analog

Reference

Input

Reference

Input

T4_Dig_Feedback

T0_DPLL_Freq

T4_APLL_for_T0

Lock_T4_to_T0

Control

T4_DPLL_Frequency

Sts_Current_Phase

T4_Op_From_TO

8 kHz

T0_DPLL_Frequency

Control

T0_DPLL_Frequency

Control

PBO

Phase

Offset

Locking

Frequency

TO1 to TO7

TO10/TO11

Locking

Frequency

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