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ACS8530 Datasheet(PDF) 59 Page - Semtech Corporation |
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ACS8530 Datasheet(HTML) 59 Page - Semtech Corporation |
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59 / 152 page  ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 3.02/November 2005 © Semtech Corp. Page 59 www.semtech.com ACS8530 SETS Address (hex): 05 Register Name sts_interrupts Description (R/W) Bits [7:0] of the interrupt status register. Default Value 1111 1111 Bit 7Bit 6 Bit 5Bit 4 Bit 3 Bit 2Bit 1Bit 0 I8 I7 I6 I5 I4 I3 I2 I1 Bit No. Description Bit Value Value Description 7 I8 Interrupt indicating that input I8 has become valid (if it was invalid), or invalid (if it was valid). Latched until reset by software writing a 1 to this bit. 0 1 Input I8 has not changed status (valid/invalid). Input I8 has changed status (valid/invalid). Writing 1 resets the input to 0. 6 I7 Interrupt indicating that input I7 has become valid (if it was invalid), or invalid (if it was valid). Latched until reset by software writing a 1 to this bit. 0 1 Input I7 has not changed status (valid/invalid). Input I7 has changed status (valid/invalid). Writing 1 resets the input to 0. 5 I6 Interrupt indicating that input I6 has become valid (if it was invalid), or invalid (if it was valid). Latched until reset by software writing a 1 to this bit. 0 1 Input I6 has not changed status (valid/invalid). Input I6 has changed status (valid/invalid). Writing 1 resets the input to 0. 4 I5 Interrupt indicating that input I5 has become valid (if it was invalid), or invalid (if it was valid). Latched until reset by software writing a 1 to this bit. 0 1 Input I5 has not changed status (valid/invalid). Input I5 has changed status (valid/invalid). Writing 1 resets the input to 0. 3 I4 Interrupt indicating that input I4 has become valid (if it was invalid), or invalid (if it was valid). Latched until reset by software writing a 1 to this bit. 0 1 Input I4 has not changed status (valid/invalid). Input I4 has changed status (valid/invalid). Writing 1 resets the input to 0. 2 I3 Interrupt indicating that input I3 has become valid (if it was invalid), or invalid (if it was valid). Latched until reset by software writing a 1 to this bit. 0 1 Input I3 has not changed status (valid/invalid). Input I3 has changed status (valid/invalid). Writing 1 resets the input to 0. 1 I2 Interrupt indicating that input I2 has become valid (if it was invalid), or invalid (if it was valid). Latched until reset by software writing a 1 to this bit. 0 1 Input I2 has not changed status (valid/invalid). Input I2 has changed status (valid/invalid). Writing 1 resets the input to 0. 0 I1 Interrupt indicating that input I1 has become valid (if it was invalid), or invalid (if it was valid). Latched until reset by software writing a 1 to this bit. 0 1 Input I1 has not changed status (valid/invalid). Input I1 has changed status (valid/invalid). Writing 1 resets the input to 0. |
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