ACS8530 datasheet(89/152 Pages) SEMTECH

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ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.02/November 2005 © Semtech Corp.

Page 89

www.semtech.com

ACS8530 SETS

Address (hex):

[15:8]

Description

(R/W) Bits [15:8] of the register

used to calibrate the crystal

oscillator used to clock the

device.

Default Value

1001 1001

Bit 7Bit 6

Bit 5Bit 4

Bit 3

Bit 2Bit 1Bit 0

cnfg_nominal_frequency_value[15:8]

Bit No.

Description

Bit Value

Value Description

[7:0]

cnfg_nominal_frequency_value[15:8]

This register is used in conjunction with Reg. 3C

(cnfg_nominal_frequency_value[7:0]) to be able to

offset the frequency of the crystal oscillator by up to

+514 ppm and –771 ppm. The default value

represents 0ppm offset from 12.800 MHz.

This value is an unsigned integer.

The value in Reg. 3C/3D is used within the DPLL to

offset the frequency value used in the DPLL only.

This means that the value programmed will affect

the value reported in the

sts_current_DPLL_frequency (Reg 07/0D/0C). It

will also affect the value programmed into

holdover_frequency_value in the

cnfg_holdover_frequency register (Reg 3E/3F/40)

and the DPLL frequency offset limit programmed

into the cnfg_DPLL_freq_limit (Reg 41/42). It must

be noted, however, that this “calibrated” frequency

is NOT used in the frequency monitors affecting

Regs 49, 4A, 4C & 4D. These registers

(cnfg_freq_mon_threshold,

cnfg_current_freq_mon_ threshold,

sts_freq_measurement, cnfg_DPLL_soft_limit)

which all use the uncalibrated crystal frequency.

The frequency monitors can also use the clock from

the output of the DPLL by programming bit

freq_mon_clock in cnfg_monitors (Reg 48).

In order to program the ppm offset of the crystal

oscillator frequency, the value in Reg. 3C and

Reg. 3D need to be concatenated. This value is an

unsigned integer. The value multiplied by

0.0196229 dec will give the value in ppm. To

calculate the absolute value, the default 39321

(9999 hex) needs to be subtracted.

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