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ACS8530 Datasheet(PDF) 25 Page - Semtech Corporation |
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ACS8530 Datasheet(HTML) 25 Page - Semtech Corporation |
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25 / 152 page ![]() ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 3.02/November 2005 © Semtech Corp. Page 25 www.semtech.com ACS8530 SETS Jitter and Wander Transfer The ACS8530 has a programmable jitter and wander transfer characteristic. This is set by the DPLL bandwidth. The -3 dB jitter transfer attenuation point can be set in the range from 0.5 mHz to 70 Hz in 18 steps. The wander and jitter transfer characteristic is shown in Figure 8. Wander on the local oscillator clock will not have a significant effect on the output clock whilst in Locked mode, provided that the DPLL bandwidth is set high enough so that the DPLL can compensate quickly enough for any frequency changes in the crystal. In Free-run or Holdover mode wander on the crystal is more significant. Variation in crystal temperature or supply voltage both cause drifts in operating frequency, as does ageing. These effects must be limited by careful selection of a suitable component for the local oscillator, as specified in the section See Local Oscillator Clock. Phase Build-out Phase Build-out (PBO) is the function to minimize phase transients on the output SEC clock during input reference switching. If the currently selected input reference clock source is lost (due to a short interruption, out of frequency detection, or complete loss of reference) the second, next highest priority reference source will be selected, and a PBO event triggered. ITU-T G.813[11] states that the maximum allowable short- term phase transient response, resulting from a switch from one clock source to another, with Holdover mode entered in between, should be a maximum of 1 µs over a 15 second interval. The maximum phase transient or jump should be less than 120 ns at a rate of change of less than 7.5 ppm and the Holdover performance should be better than 0.05 ppm. The ACS8530 performance is well within this requirement. The typical phase disturbance on clock reference source switching will be less than 5 ns on the ACS8530.The PBO requirement, as specified in Telcordia GR-1244-CORE[19], Section 5.7, is that a phase transient of greater than 3.5 µs occurring in less than 0.1 seconds should be absorbed for Stratum 3E level clocks. The ACS8530 can be configured to trigger a PBO event on an input phase transient of between 1 and 3.5 µs, programmable, via Reg. 76. The PBO operation can be set to operate automatically or it can operate under external control. For example an input phase jump of > 1 to 3.5 µs could be absorbed automatically or just flagged by the device with an interrupt raised, the external processor can then decide when and whether to perform a PBO event to absorb the phase disturbance. The monitoring block for detecting Figure 8 TO DPLL Wander and Jitter Measured Transfer Characteristics (Jitter = 0.2 UI p-p) |
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