ACS8530 datasheet(83/152 Pages) SEMTECH

83 / 152 page

ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.02/November 2005 © Semtech Corp.

Page 83

www.semtech.com

ACS8530 SETS

Address (hex):

Description

(Bit 1 RO, otherwise R/W)

modes of the device.

Default Value

1100 0010*

Bit 7Bit 6

Bit 5Bit 4

Bit 3

Bit 2Bit 1Bit 0

auto_extsync_

phalarm_time-

out

XO_edge

man_holdover

extsync_en

ip_sonsdhb

master_slaveb

reversion_mode

Bit No.

Description

Bit Value

Value Description

auto_extsync_en

Bit to enable automatic enabling of the external

Frame Sync input when locked to source defined in

Reg. 7C[3:0] (Sync_reference_source).

External Frame Sync enabled/disabled according to

extsync_en.

External Frame Sync enabled if extsync_en = 1 AND

T0 DPLL locked to source assigned to

Sync_reference_source.

phalarm_timeout

Bit to enable the automatic time-out facility on

phase alarms. When enabled, any source with a

phase alarm set will have its phase alarm cancelled

after 128 seconds.

Phase alarms on sources only cancelled by

software.

Phase alarms on sources automatically time out.

XO_edge

If the 12.800 MHz oscillator module connected to

REFCLK has one edge faster than the other, then for

jitter performance reasons, the faster edge should

be selected. This bit allows either the rising edge or

the falling edge to be selected.

Device uses the rising edge of the external

oscillator.

Device uses the falling edge of the external

oscillator.

man_holdover

Bit to select whether or not the Holdover frequency

is taken directly from Reg. 3E/Reg. 3F/Reg. 40

(cnfg_holdover_frequency). If this bit is set then it

overrides any other Holdover control bits.

Holdover frequency is determined automatically.

Holdover frequency is taken from

cnfg_holdover_frequency register.

extsync_en

Bit to select whether or not the T0 DPLL will look for

a reference Sync pulse on the SYNC2K input pin.

Even though this bit may enable the external Sync

reference, it may be disabled according to

auto_extsync_en.

No external Sync signal- SYNC2K pin ignored.

External Sync derived from SYNC2K pin according

to auto_extsync_en.

ip_sonsdhb

Bit to configure input frequencies to be either

SONET or SDH derived. This applies only to

selections of 0001 (bin) in the

cnfg_ref_source_frequency registers when the

input frequency is either 1544 kHz or 2048 kHz.

of the SONSDHB pin at power-up.

Note...this bit affects the SONET/SDH output on

TO9-refer to Reg. 64 Bit 4 and Reg. 35 Bit 4.

*The default value of this bit is taken from the value

of the SONSDHB pin at power-up.

SDH- inputs set to 0001 expected to be 2048 kHz.

SONET- inputs set to 0001 expected to be

1544 kHz.

ACS8530 Datasheet(PDF) 83 Page - Semtech Corporation

ACS8530 Datasheet(HTML) 83 Page - Semtech Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL