ACS8530 datasheet(19/152 Pages) SEMTECH

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ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.02/November 2005 © Semtech Corp.

Page 19

www.semtech.com

ACS8530 SETS

Manual Mode

(Reg. 34 Bit 4, cnfg_input_mode, man_holdover set

High.) The Holdover frequency is determined by the value

in register cnfg_holdover_frequency (Reg. 3E, Reg. 3F,

and part of Reg. 40). This is a 19-bit signed number, with

a LSB resolution of 0.0003068 ppm, which gives an

adjustment range of ±80 ppm. This value can be derived

from a reading of the register

sts_current_DPLL_frequency (Reg. 0D, Reg. 0C and

Reg. 07), which gives, in the same format, an indication of

the current output frequency deviation, which would be

read when the device is locked. If required, this value

could be read by external software and averaged over

time. The averaged value could then be fed to the

cnfg_holdover_frequency register, ready for setting the

averaged frequency value when the device enters

Holdover mode. The sts_current_DPLL_frequency value

is internally derived from the Digital Phase Locked Loop

(DPLL) integral path, which represents a short-term

average measure of the current frequency, depending on

the locked loop bandwidth (Reg. 67) selected.

It is also possible to combine the internal averaging filters

with some additional software filtering. For example the

internal fast filter could be used as an anti-aliasing filter

and the software could further filter this before

determining the actual Holdover frequency. To support

this feature, a facility to read out the internally averaged

frequency has been provided. By setting Reg. 40, Bit 5,

cnfg_holdover_modes, read_average, the value read

back from the cnfg_holdover_frequency register will be

the filtered value. The filtered value is available

regardless of what actual Holdover mode is selected.

Clearly this results in the register not reading back the

data that was written to it.

Example: Software averaging to eliminate temperature drift.

Select Manual Holdover mode by setting Reg. 34 Bit 4,

cnfg_input_mode, man_holdover High.

Select Fast Holdover Averaging mode by setting Reg. 40

Bit 6, cnfg_holdover_modes, auto_averaging High and

Reg. 40 Bit 7 High.

Select to be able to read back filtered output by setting

Reg. 40 Bit 5, cnfg_holdover_modes, read_average High.

Software periodically reads averaged value from the

cnfg_holdover_frequency register and the temperature

(not supplied from ACS8530). Software processes

frequency and temperature and places data in software

look-up table or other algorithm. Software writes back

appropriate averaged value into the

cnfg_holdover_frequency register.

Once Holdover mode is entered, software periodically

updates the cnfg_holdover_frequency register using the

temperature information (not supplied from ACS8530).

Mini-holdover Mode

Holdover mode so far described refers to a state to which

the internal state machine switches as a result of activity

or frequency alarms, and this state is reported in Reg. 09.

To avoid the DPLL’s frequency being pulled off as a result

of a failed input, then the DPLL has a fast mechanism to

freeze its current frequency within one or two cycles of the

input clock source stopping. Under these circumstances

the DPLL enters Mini-holdover mode; the Mini-holdover

frequency used being determined by Reg. 40, Bits [4:3],

cnfg_holdover_modes, mini_holdover_mode.

Mini-holdover mode only lasts until one of the following

happens:

A new source has been selected, or

The state machine enters Holdover mode, or

The original fault on the input recovers.

External Factors Affecting Holdover Mode

If the external OCXO frequency is varying due to

temperature fluctuations in the room, then the

instantaneous value can be different from the average

value, and then it may be possible to exceed the

0.05 ppm limit (depending on how extreme the

temperature fluctuations are). It is advantageous to

shield the OCXO to slow down frequency changes due to

drift and external temperature fluctuations.

The frequency accuracy of Holdover mode has to meet the

ITU-T, ETSI and Telcordia performance requirements. The

performance of the external oscillator clock is critical in

this mode, although only the frequency stability is

important - the stability of the output clock in Holdover is

directly related to the stability of the external oscillator.

Pre-locked2 Mode

This state is very similar to the Pre-Locked state. It is

entered from the Holdover state when a reference source

has been selected and applied to the phase locked loop.

It is also entered if the device is operating in Revertive

mode and a higher-priority reference source is restored.

The ACS8530 will spend a maximum of 100 seconds in

the Pre-locked2 mode. If the device is required to spend

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