ACS8530 datasheet(18/152 Pages) SEMTECH

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ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.02/November 2005 © Semtech Corp.

Page 18

www.semtech.com

ACS8530 SETS

Figure 5 Automatic Mode Control State Diagram (T0 DPLL)

Note...The state diagram above is for T0 DPLL only, and the 3-bit state value refers to the register sts_operating Reg. 09 Bits

[2:0] T0_DPLL_operating _mode. By contrast, the T4 DPLL has only automatic operation and can be in one of only two

possible states: “Instantaneous Automatic Holdover” with zero frequency offset (its start-up state), or “Locked”. The T4 DPLL

states are not configurable by the User and there is no “Free-run” state.

Free-run

select ref

(state 001)

(1) Reset

(3) no valid standby ref

(main ref invalid

or out of lock > 100s

(2) all refs evaluated

at least one ref valid

Pre-locked

wait for up to 100s

(state 110)

(4) valid standby ref

[main ref invalid or

(higher-priority ref valid

& in revertive mode) or

out of lock > 100s]

(5) selected ref

phase locked

Locked

keep ref

(state 100)

Lost-phase

wait for up to 100s

(state 111)

(10) selected source

phase locked

(6) no valid standby ref

main ref invalid

(7) phase lost

on main ref

(8) phase

regained

within 100s

(9) valid standby ref

[main ref invalid or

(higher priority ref valid

& in revertive mode)]

Pre-locked2

wait for up to 100s

(state 101)

Holdover

select ref

(state 010)

(12) valid standby ref

(main ref invalid

or out of lock >100s)

(11) no valid standby ref

(main ref invalid

or out of lock >100s)

(15) valid standby ref

[main ref invalid or

(higher-priority ref valid

& in revertive mode) or

out of lock >100s]

(13) no valid standby ref

(main ref invalid

or out of lock >100s)

(14) all refs evaluated

at least one ref valid

Reference sources are flagged as valid when

active, in-band and have no phase alarm set.

All sources are continuously checked for

activity and frequency

Only the main source is checked for phase.

A phase lock alarm is only raised on a

reference when that reference has lost phase

whilst being used as the main reference. The

micro-processor can reset the phase lock

alarm.

A source is considered to have phase locked

when it has been continuously in phase lock

for between 1 and 2 seconds.

F8530D_018AutoModeContStateDia_02

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