ACS8530 datasheet(32/152 Pages) SEMTECH

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ADVANCED COMMUNICATIONS

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DATASHEET

Revision 3.02/November 2005 © Semtech Corp.

Page 32

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ACS8530 SETS

Sync OC-N rates), then the FrSync output will still align

with the 19.44 MHz output but not with the 6.48 MHz

output clock.

The FrSync and MFrSync outputs always come from the

T0 DPLL path. 2kHz and 8kHz outputs can also be

produced at the TO1 to TO7 outputs. These can come

from either the T0 DPLL or from the T4 DPLL, controlled

by Reg. 7A, Bit 7.

If required, this allows the T4 DPLL to be used as a

separate PLL for the FrSync and MFrSync path with a

2kHz input and 2kHz and 8kHz Frame Sync outputs.

Output Clock Ports

The device supports a set of main output clocks, T0 and

T4, and a pair of secondary Sync outputs, FrSync and

MFrSync. The two main output clocks, T0 and T4, are

independent of each other and are individually selectable.

The two secondary output clocks, FrSync and MFrSync,

are derived from either T0 or T4. The frequencies of the

main output clocks are selectable from a range of pre-

defined spot frequencies and a variety of output

technologies are supported, as defined in Table 12.

PECL/LVDS/AMI Output Port Selection

The choice of PECL or LVDS compatibility is programmed

via the cnfg_differential_outputs register, Reg. 3A.

AMI port, TO8, supports a composite clock, consisting of a

64 kHz AMI clock with 8 kHz boundaries marked by

deliberate violations of the AMI coding rules, as specified

in ITU recommendation G.703[6]. Departures from the

nominal pattern are detected within the ACS8530, and

may cause reference-switching if too frequent. See “DC

Characteristics: AMI Input/Output Port” on page 139., for

more details.

Output Frequency Selection and Configuration

The output frequency at many of the outputs is controlled

by a number of inter-dependent parameters. These

parameters control the selections within the various

blocks shown in Figure 11.

The ACS8530 contains two main DPLL/APLL paths. Whilst

they are largely independent, there are a number of ways

in which these two structures can interact. Figure 11

shows an expansion of the original Block Diagram

(Figure 1) for the PLL paths.

T0 DPLL and APLLs

The T0 DPLL always produces 77.76 MHz regardless of

either the reference frequency (frequency at the input pin

of the device) or the locking frequency (frequency at the

input of the DPLL Phase and Frequency Detector (PFD)).

The input reference is either passed directly to the PFD or

via a pre-divider (not shown) to produce the reference

input. The feedback 77.76 MHz is either divided or

synthesized to generate the locking frequency.

Digital Frequency Synthesis (DFS) is a technique for

generating an output frequency using a higher frequency

system clock (204.8 MHz in the case of the 77.76 MHz

synthesis). However, the edges of the output clock are not

ideally placed in time, since all edges of the output clock

will be aligned to the active edge of the system clock. This

will mean that the generated clock will inherently have

jitter on it equivalent to one period of the system clock.

The T0 77M forward DFS block uses DFS clocked by the

204.8 MHz system clock to synthesize the 77.76 MHz

and, therefore, has an inherent 4.9 ns of p-p jitter. There

is an option to use an APLL, the T0 feedback APLL, to filter

out this jitter before the 77.76 MHz is used to generate

the feedback locking frequency in the T0 feedback DFS

block. This analog feedback option allows a lower jitter

(<1 ns) feedback signal to give maximum performance.

The digital feedback option is present so that when the

output path is switched to digital feedback the two paths

remain synchronized.

The T0 77M forward DFS block is also the block that

handles Phase Build-out and any phase offset

programmed into the device. Hence, the T0 77M forward

DFS and the T0 77M output DFS blocks are locked in

frequency but may be offset in phase.

The T0 77M output DFS block also uses the 204.8 MHz

system clock and always generates 77.76 MHz for the

output clocks (with inherent 4.9 ns of jitter). This is fed to

another DFS block and to the T0 output APLL. The low

frequency T0 LF output DFS block is used to produce

three frequencies; two of them, Digital1 and Digital2, are

available for selection to be produced at outputs TO1-

TO7, and the third frequency can produce multiple

E1/DS1 rates via the filtering APLLs. The input clock to

the T0 LF output DFS block is either 77.76 MHz from the

T0 output APLL (post jitter filtering) or 77.76 MHz direct

from the T0 77M output DFS. Utilizing the clock from the

T0 output APLL will result in lower jitter outputs from the

T0 LF output DFS block.

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