ACS8530 datasheet(12/152 Pages) SEMTECH

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ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.02/November 2005 © Semtech Corp.

Page 12

www.semtech.com

ACS8530 SETS

Notes: (i) TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being

77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz (SONET)/2.048 MHz (SDH), 6.48 MHz,

19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH input rate is selected via Reg. 34 Bit 2, ip_sonsdhb).

(ii) PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz (and 311.04 MHz for TO6 only).

(iii) Input port I11 is set at priority 12 on the Master SETS IC and priority 1 on the Slave SETS IC, as default on power up (or PORB). The

default setup of Master or Slave I11 priority is determined by the MSTSLVB pin.

Clock Quality Monitoring

Clock quality is monitored and used to modify the priority

tables of the local and remote ACS8530 devices. For each

input, the following parameters are monitored:

1. Activity (toggling).

2. Frequency (this monitoring is only performed when

there is no irregular operation of the clock or loss of

clock condition).

In addition, input ports I1 and I2 carry AMI-encoded

composite clocks which are monitored by the AMI-

decoder blocks. Loss of signal is declared by the decoders

when either the signal amplitude falls below +0.3 V or

there is no activity for 1 ms.

Any reference source that suffers a loss-of-activity or

clock-out-of-band condition will be declared as

unavailable.

Clock quality monitoring is a continuous process which is

used to identify clock problems. There is a difference in

dynamics between the selected clock and the other

reference clocks. Anomalies occurring on non-selected

reference sources affect only that source's suitability for

selection, whereas anomalies occurring on the selected

clock could have a detrimental impact on the accuracy of

the output clock.

Anomalies detected by the activity detector are integrated

in a Leaky Bucket Accumulator (one per input channel).

Occasional anomalies do not cause the Accumulator to

cross the alarm setting threshold, so the selected

reference source is retained. Persistent anomalies cause

the alarm setting threshold to be crossed and result in the

selected reference source being rejected.

Anomalies on the currently locked-to input reference

clock, whether affecting signal purity or signal frequency,

could induce jitter or frequency offsets in the output clock,

leading to anomalous behavior. Anomalies on the

selected clock, therefore, have to be detected as they

occur and the phase locked loop must be temporarily

isolated until the clock is once again pure. The clock

monitoring process cannot be used for this because the

high degree of accuracy required dictates that the

process be slow. To achieve the immediacy required by

the phase locked loop requires an alternative

mechanism. The phase locked loop itself contains a fast

activity detector such that within approximately two

missing input clock cycles, a no-activity flag is raised and

the DPLL is frozen in Holdover mode. This flag can also be

read as the main_ref_failed bit (from Reg. 06, Bit 6) and

can be set to indicate a phase lost state by enabling

Reg. 73, Bit 6. With the DPLL in Holdover mode it is

isolated from further disturbances. If the input becomes

available again before the activity or frequency monitor

rejection alarms have been raised, then the DPLL will

continue to lock to the input, with little disturbance. In this

scenario, with the DPLL in the “locked” state, the DPLL

uses “nearest edge locking” mode (±180° capture)

avoiding cycle slips or glitches caused by trying to lock to

an edge 360° away, as would happen with traditional

PLLs.

Activity Monitoring

The ACS8530 has a combined inactivity and irregularity

monitor. The ACS8530 uses a Leaky Bucket Accumulator,

which is a digital circuit which mimics the operation of an

analog integrator, in which input pulses increase the

output amplitude but die away over time. Such integrators

I13

1101

TTL/CMOS

Up to 100 MHz (see Note (i))

Default (SONET): 1.544 MHz Default (SDH): 2.048 MHz

I14

1110

TTL/CMOS

Up to 100 MHz (see Note (i))

Default (SONET): 1.544 MHz Default (SDH): 2.048 MHz

Table 4 Input Reference Source Selection and Priority Table (cont...)

Port Number

Channel

Number (Bin)

Input Port

Technology

Frequencies Supported

Default

Priority

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